This invention relates to a method of making transistors using a shadow mask. In another aspect, this invention relates to transistors comprising a shadow mask.
Traditionally, photolithography has been used for patterning transistors and circuits. The use of photolithography is undesirable, however, for low-cost, large-area applications because of its relatively high cost. Therefore, there has been an increasing effort in developing low-cost patterning techniques. Various patterning techniques have been proposed for low-cost, large-area applications, including printing methods and the use of mechanical shadow masks, but they can be problematic.
Known mechanical shadow mask techniques typically use a predefined/preformed system of mask levels. Each mask level must be precisely positioned so that it aligns with the previous layer. Registering rigid shadow masks within a desired level of accuracy (usually about 5 xcexcm) over a web-handled substrate can be difficult in a low-cost, high-throughput environment.
In addition, depending upon processing conditions and substrate material, a transistor substrate may dilate or shrink during processing. If the substrate""s size changes beyond some critical value, subsequent shadow mask levels can no longer be registered to those already on the substrate. Although this problem can be avoided by using a dynamic patterning process or by designing large tolerances into a rigid shadow mask, neither solution is ideal. Dynamic patterning processes can be costly and slow, and large design tolerances can ultimately reduce the performance of the circuits.
In view of the foregoing, we recognize that there is a need for an economical method of patterning transistors for low-cost, large-area applications that eliminates the difficulty of aligning multiple levels. Furthermore, we recognize that it would be advantageous to have a shadow mask that deforms simultaneously with the substrate during processing.
Briefly, in one aspect, the present invention provides a method for patterning transistors using a stationary shadow mask (that is, a shadow mask that is stationary with respect to the substrate). The method comprises depositing source electrode and drain electrode features onto a substrate (that is, directly onto the substrate or onto another feature or layer that is on the substrate) through a single aperture in a stationary shadow mask, the aperture having at least two opposing edges; wherein the shapes of the features are defined by the aperture and location of source materials in relation to the substrate. Preferably, the shadow mask is permanently affixed to the substrate; more preferably, the shadow mask is permanently affixed to the substrate and the shadow mask is made of a material that has a lower modulus of elasticity than the substrate material.
It has been discovered that the above-described method avoids the issue of misregistration of transistor feature layers by using a single shadow mask to define each layer. On a web-handled substrate, the use of a single shadow mask to define each transistor results in a reduction in the number of alignment steps required, thus increasing throughput. In addition, at least some of the methods of the invention provide a patterning technique that uses a permanently affixed shadow mask. These shadow masks are not susceptible to problems caused by shrinkage or dilation of the substrate during processing because they deform simultaneously with the substrate.
Thus, the method aspects of the invention meet the need in the art for an economical way to pattern transistors for low-cost, large-area applications that eliminates the difficulty of aligning multiple feature levels.
In other aspects, this invention provides a method for depositing n-channel and p-channel complementary semiconductor materials adjacent to each other for use in complementary transistor circuit elements such as a metal oxide semiconductor (CMOS) element. This method comprises forming gate electrode, gate dielectric, source electrode, and drain electrode features on a substrate and depositing a first semiconductor material and a second semiconductor material through a single aperture in a stationary shadow mask, the aperture having at least two opposing edges, such that at least a portion of each of the semiconductor materials does not overlap the other semiconductor material. This method eliminates the difficulties associated with aligning multiple feature levels of transistors using multiple masks.
In still other aspects, this invention also provides articles comprising a transistor comprising a shadow mask permanently affixed to a substrate, and devices comprising the articles.